Strategies and Software Support for the Management of Hardware Performance Counters

Stefano CarnĂ , Romolo Marotta, Alessandro Pellegrini, and Francesco Quaglia

Published in: Software: Practice and Experience, 2023
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Hardware Performance Counters (HPCs) are facilities offered by most off-the-shelf CPU architectures. They are a vital support to post-mortem performance profiling and are exploited by standard tools such as Linux or Intel V-Tune. Nevertheless, an increasing number of application domains (e.g., simulation, task-based high-performance computing, or cybersecurity) are exploiting them to perform different activities, such as self-tuning, autonomic optimization, and\slash or system inspection. This repurposing of HPCs can be difficult, e.g., because of the overhead for extracting relevant information. This overhead might render any online or self-tuning activity ineffective. This article discusses various practical strategies to exploit HPCs beyond post-mortem profiling, suitable for different application contexts. The presented strategies are accompanied by a general primer on HPCs usage on Linux. We also provide reference x86 (both Intel and AMD) implementations targeting the Linux kernel, upon which we present an experimental assessment of the viability of our proposals.

BibTeX Entry:

author = {CarnĂ , Stefano and Marotta, Romolo and Pellegrini, Alessandro and Quaglia, Francesco},
title = {Strategies and Software Support for the Management of Hardware Performance Counters},
journal = {Software: Practice and Experience},
year = {2023},
month = jul,
volume = {53},
issue = {10},
pages = {1928--1957},
issn = {1097-024X},
doi = {10.1002/spe.3236},
publisher = {Wiley},
series = {SPE}