Detecting Cache-based Side Channel Attacks using Hardware Performance Counters

Serena Ferracci

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The remainder of this thesis is organized as follows. Chapter 2 provides an overview of optimization techniques introduced in order to speed up executions. The advantages and the disadvantages implicated by the optimization and the families of attacks that exploit them to read and/or write memory of the victim process are also discussed. Chapter 3 presents the hardware facilities used to detect the described attacks. Chapter 4 explains the methodology used to detect the attack techniques presented and how PMCs can be used for this purpose. Chapter 5 describes a possible implementation of the methodology. Finally, Chapter 6 concludes and sums up this thesis and discusses some possible future works. It discloses how our proposal can be enhanced for an extended support and possible directions for future work.

BibTeX Entry:

author = {Ferracci, Serena},
school = {Sapienza, University of Rome},
title = {Detecting Cache-based Side Channel Attacks using Hardware Performance Counters},
year = {2019},
type = {mathesis},
comment = {Supervisor: A. Pellegrini - Co-Supervisor: S. CarnĂ }