Analysis of Manufacturing Yields Evaluation of VLSI/WSI Systems: Methods and Methodologies
Gianluca Battaglini
Abstract:
BibTeX Entry:
@phdthesis{tBatt98,
author = {Battaglini, Gianluca},
school = {Sapienza, University of Rome},
title = {Analysis of Manufacturing Yields Evaluation of VLSI/WSI Systems: Methods and Methodologies},
year = {1998},
type = {phdthesis},
comment = {Supervisor: B. Ciciani}
}
author = {Battaglini, Gianluca},
school = {Sapienza, University of Rome},
title = {Analysis of Manufacturing Yields Evaluation of VLSI/WSI Systems: Methods and Methodologies},
year = {1998},
type = {phdthesis},
comment = {Supervisor: B. Ciciani}
}